Design model for fully integrated high-performance linear CMOS power amplifiers


A model for fully integrated CMOS linear power amplifiers (PAs) is presented. The model predicts the performance of the CMOS PA in terms of power-added efficiency (PAE) and output power (P-OUT) with respect to the main design parameters, such as supply voltage, current consumption, gain and inductor quality factors (Qs). In order to demonstrate the usefulness of the model, several studies showing the impact of these design parameters on the PA performance are presented. Finally, a 0.18 mu m fully integrated CMOS PA has been fabricated and compared with the model, showing good agreement. The fabricated PA presents 23 dBm of 1 dB compression point (P-1dB) and 27 dBm of saturated power (P-SAT) at 4.2 GHz with high maximum PAE of 32%.